In data processing systems it is conventional to utilize a single central processor unit (CPU) with a single memory system with appropriate conrol logic in the CPU for controlling the transfer of address and data information between such units on suitable buses. In the design thereof it is desirable to arrange the logic control so that a processor is capable of operating with a memory unit even when the cycle time of operation is not the same as the cycle time of operation of the central processor unit, i.e., the CPU and memory timing are not exactly synchronous and the CPU can operate, for example, with memory units having different speeds of operation. Such non-synchronous operation is often most effectively arranged so that the CPU and memory operating time cycles are not completely asynchronous but rather are quasi-synchronous, i.e., there is a defined phase, or time, relation between them. One such system has been described in U.S. Pat. No. 4,014,006, issued to Sorensen et al.
In making the most effective use of such a quasisynchronous system it is desirable that the speed of operation of the overall system be reduced as much as possible by providing for simultaneous operation of more than one memory module so that access to a second module can be obtained not only before the first memory module has completed its rewrite cycle of operation, but even before the first module has completed its data transfer.
Further, since the design and fabrication of memory units is generally relatively more expensive than the design and fabrication of central processor units, one approach to reducing the overall costs of data processing systems is to provide access to a memory sub-system by more than one central processor unit. If a single memory unit is made available to multiple CPUs and appropriate address and data information transfers can be efficiently arranged and controlled at relatively little increase in cost and equipment, the overall effectiveness of operation as a function of cost can be considerably enhanced. Moreover, since only one section of memory is active at a time, utilization of the rest of the memory system can be more fully realized if more than one processor is sharing the system (i.e., more data can be processed per unit time).